Routing in NoCs
In this work, the focus is on the application of computer networking principles and techniques in the field of high performance computer architecture (network-on-chip architectures - NoC) in order to provide efficient routing protocols. Thus, we proposed a novel, adaptive routing scheme for NoC. In particular, the proposed routing scheme decides on the output port of an incoming packet by taking into account the dynamic traffic and power consumption on neighboring router links. For that, a simple, generic, and efficient nonlinear control law is built, based on fuzzy logic control, to dynamically calculate the input links cost. Although the focus is on bufferless NoCs, it can also be applied to buffered NoCs as well. The additional digital logic required for the proposed scheme is not in the router critical path, and, therefore, imposes no additional latency. We demonstrated, via simulative evaluation of light to heavy congestion conditions, as well as hardware implementation in ASIC and FPGA technologies, that the proposed scheme outperforms representative conventional counterparts in terms of throughput and latency. Thus, the effectiveness of the proposed scheme is shown, as the performance is consistently better.